LDPC decoder chip
LDPC codes are how 5G, Wi-Fi, and satellite links survive noisy channels. Decoding one means finding a valid codeword that satisfies a set of parity constraints despite the noise. That is a combinatorial optimization problem, the same class our oscillator hardware solves, so we built a decoder out of it: AMORGOS, in TSMC 28nm.
Architecture
Each bit maps to a relaxation oscillator spin; each parity check becomes a clause. 96 spins connect to 48 parity-check clauses through twin crossbars, enabling six-body spin interactions. When parity checks are violated, feedback nudges spins toward a satisfying assignment. When all checks pass, the system freezes.
Soft information
Rather than initializing spins with hard binary values, the chip initializes spin phases based on channel confidence, guiding the system toward the correct codeword. This lets the decoder outperform belief propagation by orders of magnitude at low SNR.
Results
95 ns time-to-solution, 7.28 pJ/bit. 1,000× lower bit error rate than belief propagation at 2–5 dB SNR. Testing exceeded 100 million decoding cycles with stable operation from −20 °C to 70 °C.